34 Gb/s PDM-QPSK coherent receiver using SiGe ADCs and a single FPGA for digital signal processing - ENS de Lyon - École normale supérieure de Lyon Access content directly
Conference Papers Year : 2012

34 Gb/s PDM-QPSK coherent receiver using SiGe ADCs and a single FPGA for digital signal processing

Abstract

A fully reprogrammable coherent receiver using an integrated coherent front end, four high speed ADCs and powerful FPGAs is reported and tested against optical noise level, chromatic dispersion and PMD for various equalizer filter length.
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Dates and versions

ensl-00766801 , version 1 (19-12-2012)

Identifiers

  • HAL Id : ensl-00766801 , version 1

Cite

Eric Dutisseuil, Jean-Marc Tanguy, Adrian Voicila, Rémi Laube, Francois Bore, et al.. 34 Gb/s PDM-QPSK coherent receiver using SiGe ADCs and a single FPGA for digital signal processing. Optical Fiber Communication Conference, Mar 2012, nc, United States. pp.OM3H.7. ⟨ensl-00766801⟩
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