Floating-point operators on FPGAs do not have to be identical to the ones available in processors. This article studies two common situations where the flexibility of FPGAs allows one to design application-specific floating-point operators. First, for applications involving the addition of a large number of floating-point values, an ad-hoc accumulator is proposed. By tailoring its parameters to the numerical requirements of the application, it can be made arbitrarily accurate, at an area cost comparable in practice to a standard floating-point adder, and at a higher frequency. The second example is the sum-of-product operation, which is the building block of matrix computations. An architecture is proposed based on the previous accumulator and an ad-hoc rounding-free multiplier. These architectures are implemented within the FloPoCo generator, freely available under the GPL.