An FPGA architecture for solving the Table Maker's Dilemma
Résumé
Solving the Table Maker's Dilemma, for a given function and a given target floating-point format, requires testing the value of the function, with high precision, at a very large number of consecutive values. We give an algorithm that allows for performing such computations on a very regular architecture, and present an FPGA implementation of that algorithm.
| Origine | Fichiers produits par l'(les) auteur(s) |
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